L3Harris

Job Title: Lead, Electrical Engineer – Semiconductor Silicon Interposer Design Engineer

Job Code: 9771

Job Location: Palm Bay, FL or remote

Job Description:

The L3Harris Microelectronics organization is expanding our in-house semiconductor research and development efforts and capabilities. This role will allow you to lead the Silicon Interposer Die Design team in creating new state of the art Semiconductor Fabrication designs. Your primary responsibilities will require a deep understanding of modern semiconductor design tools, rules, and processes, along with an intimate knowledge of CAD SW tool selection, operation, process flow control and analysis, identify potential design bottlenecks, and recommend efficiency improvement plans.

Essential Functions:

• Work closely with a small team to achieve and develop designs for Silicon Interposers using Cadence APD (Advanced Package Designer 23.1), Cadence Virtuoso and Cadence SCM
• Candidate will be responsible for creating and maintaining schematics, design databases, sys
• Must be able to adapt to a evolving process and work closely with teammates providing up to date changes 
• Position will require individual to interface with Cadence AE’s providing feedback on tool development and process flow. Additional skills that would be a benefit:
  • Knowledge of Silicon design technology
  • Cadence Virtuoso
  • Stream file format
  • Cadence Skill programing
• Proven experience with updating, operating, and designing with new semiconductor design CAD tools and processes
• Manages complex semiconductor interposer designs, works across multiple industry standard/non-standard die design CAD tools, develops processes, performs failure analysis investigations, RCCAs, and leads a team of senior die designers
• Create design process control documentation and mentor/lead other personnel on design rules and processes
• Ability to document, communicate, and present technical topics/recommendations/issues/concerns to internal and external customers
• Work with general oversight and lead technical team of up to 6 additional engineers and designers

Qualifications:

• Bachelor’s Degree in Industrial Engineering, Electrical Engineering, Mechanical Engineering, Chemical Engineering, Material Scientist, Physics, Chemistry, or Applied Mathematics and minimum 9 years of prior relevant experience. Graduate Degree and a minimum of 7 years of prior related experience. In lieu of a degree, minimum of 13 years of prior related experience.
• Ability to obtain a security clearance
• 7+ years of Electrical substrate design with various CAD tools and experience using Cadence APD (Advance Package designer 17.4), Cadence Virtuoso and Cadence SCM
• Experience with 3D die stacking and associated thermal, mechanical, and assembly issues related to microelectronic packaging 

Preferred Additional Skills:

• Existing Security Clearance
• Cadence APD (Advance Package designer 17.4), Cadence Virtuoso and Cadence SCM.
• Experience with the Cadence constraint manager

In compliance with pay transparency requirements, the salary range for this role in CA is $122,500.00 - $227,500.00. In compliance with pay transparency requirements, the salary range for this role in CO or remote is $106,500.00 - $197,500.00. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements.